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PCI CD/CDa Configurable DMA Interface User’s Guide Registers

EDT, Inc. May 2007 27

PCI Interrupt Status Register

Size 32-bit

I/O read-only

Address 0xC8

Access EDT_DMA_STATUS

Comment The driver uses this register initially to determine the source of a PCI interrupt.

UI Xilinx Data Register

Size 32-bit

I/O read-write

Address 0xCC

Access EDT_REMOTE_DATA

UI Xilinx Registers

The UI Xilinx is a field-programmable gate array used to implement the PCI CD/CDa interface or to

test the board. The UI Xilinx is programmed serially, using the PCI Interrupt and UI Xilinx

Configuration Register on page 26.

NOTE The following registers are defined to control the interface and reside in the UI Xilinx. In order to

access those registers, the PCI CD/CDa requires that the UI Xilinx be loaded with a program that

defines them. If the Xilinx is not loaded, or loaded with a different program, these registers are

inaccessible.

The Xilinx IC is programmed when the PCI CD/CDa driver is loaded, or by the application

program. If you have received a customized application program for your PCI CD/CDa from

Engineering Design Team, some or all of these registers may not be defined. Consult the

documentation that came with your customized program instead.

Bit PCD_ Description

16–31 not used

15 PCI_INTR PCI interrupt. When asserted, the PCI CD/CDa is asserting an interrupt on the PCI bus.

14 not used

13 RMT_INTR UI Xilinx interrupt. When asserted, the UI Xilinx interrupt is set. If bits 14 and 15 of the

the PCI interrupt and UI Xilinx configuration register are aserted, the UI Xilinx causes a

PCI interrupt.

12 DMA_INTR End of DMA interrupt. Asserted when at least one of the DMA interrupts is asserted in

the scatter-gather DMA next count and control register. Causes a PCI interrupt if bit 15

of the PCI interrupt and UI Xilinx configuration register is enabled.

11–0 not used

Bit Description

31–8 not used

7–0 Read or write data for UI Xilinx, using the address specified in EDT_RMT_ADDR (bits 0–6) of the PCI

Interrupt and UI Xilinx Configuration Register.

1 2 ... 26 27 28 29 30 31 32 33 34 35 36 ... 39 40

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